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KED Products Based on TI AM62L#

SoM Models#

Name Product # Description Delivery Settings
OSM-S AM62L DC 2GB/32GB -25..+85 °C 40099 330 AM62L SoM (2 GB RAM, 32 GB eMMC) OEM: No Boot-Fuses, No Software

Demo Kits#

Name Product # Board # Description
DK AM62L DC OSM-S 2GB/32GB 50099106 40099 339 Demo Kit (dual core, 1250 MHz, 2 GB RAM, 32 GB eMMC)

The bootloader is expected at the following offsets:

  • SD card boot: 0k (0x0000)
  • eMMC boot: 0k (0x0000)

eMMC configuration for booting from eMMC (Linux commands):

# set 8-bit boot bus interface
mmc bootbus set single_backward x1 x8 /dev/mmcblk0
# enable the mmcblk0boot0 partition with ack
mmc bootpart enable 1 1 /dev/mmcblk0

Kontron reserved area on extended OTP Memory#

The first 400 physical bits (bit 0 to 399) of the extended OTP are reserved for special usage by Kontron. These locations are already programmed with appropriate content and can't be used to store customer values! In the write view they cover row 0 to 15, in the read view MMR 0 to 12. The image below illustrates these areas

Kontron reserved area on the AM62L extended OTP: rows (write view), fields and MMRs (read view)

Row Field Bits Physical Bits MMR First … Last Data Bit Intended Usage
0 [24:0] 0–24 0 MMR0[0] … MMR1[15] MAC 1 (Port 1), 48 bit
1 [47:25] 25–49 0–1 MAC 1 (Port 1), 48 bit
2 [24:0] 50–74 1–2 MMR1[18] … MMR3[1] MAC 2 (Port 2), 48 bit
3 [47:25] 75–99 2–3 MAC 2 (Port 2), 48 bit
4 [24:0] 100–124 3 MMR3[4] … MMR4[3] KED SoM Unique ID, 32 bit
5 [31:25] 125–149 3–4 KED SoM Unique ID, 32 bit
6 [24:0] 150–174 4–5 MMR4[22] … MMR5[21] KED Board Unique ID, 32 bit
7 [31:25] 175–199 5–6 KED Board Unique ID, 32 bit
8–15 [24:0] per row 200–399 6–12 MMR6[8] … MMR12[15] Reserved

The Row and Field Bits columns are the write view — a row is programmed as a whole with fuse prog and is 25 bit wide. The MMR column is the read view: fuse read returns memory mapped registers of 32 bit, so MMR n covers the physical bits 32n to 32n+31. Because the two grids do not line up, a row usually spans two MMRs. See Fuse Configuration for extended OTP on TI AM62L for how values are programmed and read back.

Customer data may start at physical bit 400, which is row 16 for writing and MMR 13 for reading.

Layout and Connectors#

BL AM62L Connectors Layout

BL AM62L Connectors Pinout

BL i.MX93 Connector 2x4 Pin Numbers

Digital IOs#

Four digital inputs/outputs are available. The table below shows number and function of available DIOs and their associated GPIOs.

Each DIO has one GPIO that switches a MOSFET driver against the supply (24V) rail and another GPIO to read back the voltage level via a resistor divider.

DIO circuit

The GPIOs are provided by a GPIO expander which is connected via I2C.

DIO Name Function GPIO Label GPIO Device GPIO Offset Connector
DIO1 drive DIO1_OUT gpiochip2 0 X1501 - Pin 1
DIO1 read DIO1_IN gpiochip2 1 X1501 - Pin 1
DIO2 drive DIO2_OUT gpiochip2 2 X1501 - Pin 3
DIO2 read DIO2_IN gpiochip2 3 X1501 - Pin 3
DIO3 drive DIO3_OUT gpiochip2 4 X1501 - Pin 5
DIO3 read DIO3_IN gpiochip2 5 X1501 - Pin 5
DIO4 drive DIO4_OUT gpiochip2 6 X1501 - Pin 7
DIO4 read DIO4_IN gpiochip2 7 X1501 - Pin 7

Serial Devices#

The overview below shows which serial device has which name in the OS and which UART of the SoC it belongs to.

OSM Name Type Accessible via Connector
UART_A RS232 /dev/ttyS3 X1401
UART_B RS485 /dev/ttyS1 X1402
UART_CON UART/TTL (Debug UART) /dev/ttyS0 X20 (USB Mini-B)

CAN-Bus Interface#

The device has one CAN bus interface. It is present after boot, but is not enabled by default.

OSM Name Accessible via Connector
MCAN0 can0 X1402